Patent · US Active

Memory circuit

US9093126B2 · kind B2 · utility

4Cited by

15References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Chen-Lin Yang · Hengshan, TW
Kao-Cheng Lin · Taipei, TW
Chung-Hsien Hua · Hsinchu, TW

Key dates

Filing date	Jul 31, 2012
Grant date	Jul 28, 2015
Priority date	—
Expiry date	Jan 25, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/413
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.