Multi-height multi-composition semiconductor fins
US9093275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Jan 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02639
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.