Inventor · Herent, BE

Dan M. Mocuta

24Patents
8h-index
40Co-inventors
75Inventor score

Filing activity: Apr 19, 2002 → Jul 29, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6958286B2 Method of preventing surface roughening during hydrogen prebake of SiGe substrates Emerging Cross-Sectional Technologies 234 Expired
US6916698B2 High performance CMOS device structure with mid-gap metal gate Electricity 133 Expired
US7723750B2 MOSFET with super-steep retrograded island Electricity 124 Active
US7071103B2 Chemical treatment to retard diffusion in a semiconductor overlayer Electricity 120 Expired
US6762469B2 High performance CMOS device structure with mid-gap metal gate Electricity 60 Expired
US7268049B2 Structure and method for manufacturing MOSFET with super-steep retrograded island Electricity 14 Expired
US7550370B2 Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density Electricity 10 Expired
US7691698B2 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain Electricity 8 Active
US9093275B2 Multi-height multi-composition semiconductor fins Electricity 5 Active
US7528027B1 Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel Electricity 5 Active
US7202132B2 Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs Electricity 5 Expired
US6749684B1 Method for improving CVD film quality utilizing polysilicon getterer Chemistry; Metallurgy 4 Expired
US7498602B2 Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets Electricity 4 Active
US10720363B2 Method of forming vertical transistor device Electricity 4 Active
US8168971B2 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain Electricity 1 Active
US9443854B2 FinFET with constrained source-drain epitaxial region Electricity 1 Active
US9461050B2 Self-aligned laterally extended strap for a dynamic random access memory cell Electricity 0 Active
US9252215B2 Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device Electricity 0 Active
US9536879B2 FinFET with constrained source-drain epitaxial region Electricity 0 Active
US10522552B2 Method of fabricating vertical transistor device Electricity 0 Active
US9059194B2 High-K and metal filled trench-type EDRAM capacitor with electrode depth and dimension control Electricity 0 Active
US9673197B2 FinFET with constrained source-drain epitaxial region Electricity 0 Active
US9299780B2 Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device Electricity 0 Active
US11991877B2 DRAM circuitry and method of forming DRAM circuitry Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.