Device packaging with substrates having embedded lines and metal defined pads
US9093313B2 · kind B2 · utility
0Cited by
6References
3Claims
0Family size
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Key dates
| Filing date | Sep 9, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Sep 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.