Memory transistor with multiple charge storing layers and a high work function gate electrode
US9093318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Jan 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer; and a gate electrode comprising doped polysilicon formed over a surface of the ONNO stack. The MOS logic transistor includes a gate oxide and a gate electrode comprising doped polysilicon. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.