Metallic mask patterning process for minimizing collateral etch of an underlayer
US9093387B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Jan 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.