Interconnection wires of semiconductor devices
US9093501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Jul 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes forming a plurality of substantially equal-spaced first spacers having a first pitch over a substrate and forming first metal interconnecting wires utilizing the first spacers. The method also includes forming a plurality of substantially equal-spaced second spacers in such a way to abut, respectively, the plurality of first metal interconnecting wires and define a plurality of substantially equal-spaced trenches. A plurality of second metal interconnecting wires are disposed, respectively, within the trenches and the second spacers are removed, thereby defining a plurality of substantially equal-spaced channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.