Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure
US9093503B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Feb 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.