Patent · US Active

Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same

US9093550B1 · kind B1 · utility

18Cited by

413References

9Claims

0Family size

Assignee

Mie Fujitsu Semiconductor Limited · JP

Inventors

Dalong Zhao · San Jose, US
Pushkar Ranade · Los Gatos, US
Bruce McWilliams · Menlo Park, US

Key dates

Filing date	Jan 31, 2013
Grant date	Jul 28, 2015
Priority date	—
Expiry date	Jan 31, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0177
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.