Systems and methods of phase frequency detection involving features such as improved clock edge handling circuitry/aspects
US9094025B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.