High temperature equalized electrical parasitic power packaging method for many paralleled semiconductor power devices
US9095054B1 · kind B1 · utility
9Cited by
8References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Oct 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A four quadrant power module with lower substrate parallel power paths and upper substrate equidistant clock tree timing utilizing parallel leg construction in a captive fastener power module housing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.