Target and method for mask-to-wafer CD, pattern placement and overlay measurement and control
US9097989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2009 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Jan 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer. The method further includes measuring the targets on the wafer at one or more of the layers, and correlating the mask and wafer measurements to distinguish mask and lithography induced components of critical dimension and overlay variation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.