Method and apparatus for saving power by efficiently disabling ways for a set-associative cache
US9098284B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2014 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Dec 2, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.