Method for reducing memory latency in processor
US9098296B2 · kind B2 · utility
1Cited by
7References
12Claims
0Family size
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Key dates
| Filing date | Jun 17, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Dec 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing memory latency in a processor includes identifying an independent instruction (or cache miss instruction) and corresponding dependent instructions from a re-circulating issue window (RIW) when a cache miss is encountered. The cache miss instruction and corresponding dependent instructions are moved to a re-circulating issue buffer (RIB) and moved back to the RIW from the RIB for processing when the cache miss is resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.