Managing addressable memory in heterogeneous multicore processors
US9098406B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Dec 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/253
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies described herein generally describe technologies for managing addressable memories in a heterogeneous multicore chip. Technologies may be adapted to determine whether swapping a first data segment and a second data segment is suitable. The first data segment may be stored in a first addressable memory, and the second data segment may be stored in a second addressable memory. If the swapping is determined to be suitable, then the technologies may be adapted to swap the first data segment and the second data segment. As a result of the swap, the first data segment will be stored in the second addressable memory, and the second data segment will be stored in the first addressable memory. The technologies may also be adapted to update corresponding swap status indicators to indicate that the first data segment and the second data segment have moved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.