Coordinated prefetching based on training in hierarchically cached processors
US9098418B2 · kind B2 · utility
14Cited by
3References
20Claims
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Key dates
| Filing date | Mar 20, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Jul 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processors and methods for coordinating prefetch units at multiple cache levels. A single, unified training mechanism is utilized for training on streams generated by a processor core. Prefetch requests are sent from the core to lower level caches, and a packet is sent with each prefetch request. The packet identifies the stream ID of the prefetch request and includes relevant training information for the particular stream ID. The lower level caches generate prefetch requests based on the received training information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.