Determining an effective stress level on a processor
US9098561B2 · kind B2 · utility
0Cited by
22References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2011 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Jun 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.