Patent · US Active

Semiconductor package with top-side insulation layer

US9099391B2 · kind B2 · utility

0Cited by

16References

7Claims

0Family size

Assignee

Infineon Technologies Austria AG · AT

Inventors

Ralf Otremba · Kaufbeuren, DE
Jürgen Schredl · Mering, DE
Wolfgang Peinhopf · Klagenfurt, AT
Fabio Brucchi · Villach, AT
Josef Höglauer · Heimstetten, DE

Key dates

Filing date	Mar 14, 2013
Grant date	Aug 4, 2015
Priority date	—
Expiry date	Mar 14, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1815
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.