Sidewall image transfer with a spin-on hardmask
US9099401B2 · kind B2 · utility
8Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2013 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.