Three-dimensional system-level packaging methods and structures
US9099448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Mar 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/185
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.