Semiconductor device and method of forming junction enhanced trench power MOSFET
US9099519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Jan 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.