Methods of patterning small via pitch dimensions
US9099530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2014 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | May 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.