One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers

US9099647B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yu-Wen Liao · New Taipei, TW
• Wen-Ting Chu
• Kuo-Chi Tu · Baoshan, TW
• Chih-Yang Chang · 員林市, TW
• Chin-Chieh Yang · New Taipei, TW
• Hsia-Wei Chen · Taipei, TW
• Ching-Pei Hsieh

Key dates

• Filing date: Jan 28, 2015
• Grant date: Aug 4, 2015
• Expiry date: Jan 28, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.