Managing quiesce requests in a multi-processor environment
US9104513B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Mar 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1415
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to managing quiesce requests in a multi-processor system. Aspects of the embodiments include receiving a quiesce request at a quiesce controller from a requesting processor, the requesting processor being one of a plurality of processors in a multi-processor system, and determining that the quiesce request is not accepted by the quiesce controller. Aspects also include, based on the quiesce request being not accepted by the quiesce controller, generating a reject message configured to indicate that the quiesce request has been rejected, holding the reject message until a quiesce command is broadcast to the multi-processor system, the quiesce command based on a different quiesce request, and sending the reject message to the requesting processor based on the broadcast of the quiesce command being detected by the quiesce controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.