Optimizing memory bandwidth consumption using data splitting with software caching
US9104577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Apr 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor collects information for a dominant data access loop and reference code patterns based on data reference pattern analysis, and for pointer aliasing and data shape based on pointer escape analysis. The computer processor selects a candidate array for data splitting wherein the candidate array is referenced by a dominant data access loop. The computer processor determines a data splitting mode by which to split the data of the candidate array, based on the reference code patterns, the pointer aliasing, and the data shape information, and splits the data into two or more split arrays. The computer processor creates a software cache that includes a portion of the data of the two or more split arrays in a transposed format, and maintains the portion of the transposed data within the software cache and consults the software cache during an access of the split arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.