Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device
US9105317B2 · kind B2 · utility
7Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Oct 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.