Memory device and method for writing therefor
US9105326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | May 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at the first voltage level for a first predetermined duration. The voltage level at the power terminal of the memory cell is maintained at a second voltage level for a second predetermined duration, where the second voltage level is between the first voltage level and the supply voltage level. During the write cycle, the voltage level at the power terminal of the memory cell is caused to change from the first voltage level toward the supply voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.