Gate strain induced work function engineering

US9105498B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Mohit Bajaj · Savanuru, IN
• Kota V. R. M. Murali · Bengaluru, IN
• Rahul Nayak · Waynesboro, US
• Edward J. Nowak · South Burlington, US
• Rajan K. Pandey · Bengaluru, IN

Key dates

• Filing date: Mar 1, 2012
• Grant date: Aug 11, 2015
• Expiry date: Nov 4, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.