Copper feature design for warpage control of substrates
US9105535B2 · kind B2 · utility
5Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2012 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Jun 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer that includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.