Electronic device and method for fabricating the same
US9105840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Mar 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.