Patent · US Active

High throughput finite state machine

US9110524B1 · kind B1 · utility

5Cited by

6References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Weirong Jiang · San Jose, US
Gordon J. Brebner · Monte Sereno, US
Yi-Hua Edward Yang · San Jose, US

Key dates

Filing date	Jun 9, 2014
Grant date	Aug 18, 2015
Priority date	—
Expiry date	Jun 9, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG05B2219/23289
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.