Supporting targeted stores in a shared-memory multiprocessor system
US9110718B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2012 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jan 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present embodiments provide a system for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor in the shared-memory multiprocessor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. The system includes an interface, such as an application programming interface (API), and a system call interface or an instruction-set architecture (ISA) that provides access to a number of mechanisms for supporting targeted stores. These mechanisms include a thread-location mechanism that determines a location near where a thread is executing in the shared-memory multiprocessor, and a targeted-store mechanism that targets a store to a location (e.g., cache memory) in the shared-memory multiprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.