RAM-based ternary content addressable memory
US9111615B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90339
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is disclosed that includes one or more TCAM memory units, each configured to store a respective set of rules. Each unit has an input coupled to receive an input search key from an input of the memory and includes a plurality of stages 1 through H. Each stage is configured to receive a respective multi-bit segment of the input search key and provide a result segment in response thereto. The result segment includes, for each rule of the respective set of rules, a bit that indicates whether or not the rule matches the segment of the input search key. Each unit also includes a first output circuit configured to generate a combined result indicating which rules match all of the respective segments received by each of the plurality of stages. The memory can also include one or more update circuits to update rules in a plurality of units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.