Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods
US9111635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jul 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.