Differential latch word line assist for SRAM
US9111637B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | May 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.