Redundancy schemes for non-volatile memory based on physical memory layout
US9111648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jun 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.