Semiconductor structure and layout structure for memory devices
US9111796B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.