Hierarchical arbitration
US9117022B1 · kind B1 · utility
6Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2012 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Jul 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for increasing speed and reducing area for arbitration logic in an integrated circuit (IC) are provided. For example, in one embodiment, a method includes arbitrating at least one master request in a first level of arbitration blocks. A second level of arbitration blocks arbitrates at least two arbitration blocks from the first level. A first level of multiplexers multiplex at least one master payload based at least in part upon the arbitration of the first level of arbitration blocks. A second level of multiplexers multiplex at least two signals propagated from the first level of multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.