High density field effect transistor design including a broken gate line
US9117051B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 21, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Feb 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.