Methods for manufacturing semiconductor devices

US9117777B2 · kind B2 · utility

Assignee

• IMEC · BE

Inventors

• Benjamin Vincent · San Francisco, US
• Geert Eneman · Heverlee, BE

Key dates

• Filing date: Dec 13, 2013
• Grant date: Aug 25, 2015
• Expiry date: Dec 13, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/762
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.