Device with engineered epitaxial region and methods of making same
US9117843B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2011 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Mar 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.