Method for incorporating impurity element in EPI silicon process
US9117905B2 · kind B2 · utility
7Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2009 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Jul 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.