Patent · US Active

Scheme to improve the performance and reliability in high voltage IO circuits designed using low voltage devices

US9118315B2 · kind B2 · utility

2Cited by

1References

21Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Venkateswara Reddy P · Bengaluru, IN
Vinayak Ghatawade · Savanuru, IN

Key dates

Filing date	Sep 24, 2014
Grant date	Aug 25, 2015
Priority date	—
Expiry date	Sep 24, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/01714
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO circuit includes a pre-reverse switch, a main-driver and a post-reverse switch. The pre-reverse switch includes a first capacitor and a second capacitor. The main-driver includes a first parasitic capacitance and a second parasitic capacitance. The post-reverse switch includes a third capacitor and a fourth capacitor. The first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic capacitance on the second bias voltage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.