Channel estimation in wireless communication
US9118515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | May 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/2618
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A channel estimation processor for a receiver in a wireless communication system is described. The channel estimation processor includes a stage-1 processor (STG1) arranged to pluralities of Nsym reference symbol correlation values per slot. The channel estimation processor includes a stage-2 processor (STG2) comprising a plurality of stage-2a processors for obtaining filtered outputs per slot, a respective plurality of stage-2b processors for obtaining respective slot filter results and a stage-2 adder (STG2ADD) for obtaining channel estimates for respective anchor positions. The stage-2a processors are arranged to filter respective pluralities of reference symbol correlation values using respective reference symbol filters (ga) to obtain a respective filtered output per slot. The stage-2b processors (STG2B1) are arranged to filter a predetermined number of Nslots associated filtered reference outputs using respective slot filters (a) with respective slot-specific filter coefficients (ai) to obtain a first slot filter result. The stage-2 adder (STG2ADD) is arranged to sum the slot filter results to obtain the channel estimate for anchor symbol positions. An interpolator is arrange…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.