Bimodal branch predictor encoded in a branch instruction
US9122486B2 · kind B2 · utility
4Cited by
6References
22Claims
0Family size
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Key dates
| Filing date | Nov 8, 2010 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Jan 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.