High performance system that includes reconfigurable protocol tables within an ASIC wherein a first protocol block implements an inter-ASIC communications protocol and a second block implements an intra-ASIC function
US9122816B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Nov 14, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.