Semiconductor apparatus
US9123396B2 · kind B2 · utility
1Cited by
0References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Aug 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.