SRAM write-assisted operation with VDD-to-VCS level shifting
US9123439B2 · kind B2 · utility
17Cited by
9References
17Claims
0Family size
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Key dates
| Filing date | Nov 22, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Jan 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit and a method for driving data writes to an SRAM bit cell in an electronic circuit. The electronic circuit translates a first write signal in a lower voltage domain to a second write signal in a higher voltage domain. Based, at least in part, on the second write signal, the electronic circuit controls a discharge of a voltage of a data write line to a ground voltage level. The electronic circuit provides a negative voltage boost to the data write line after the voltage of the data write line has been discharged to reach or exceed a threshold value relative to the ground voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.