Overlay abnormality gating by Z data
US9123583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Nov 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B2210/56
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.