Method of forming drain extended MOS transistors for high voltage circuits
US9123642B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Jan 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.